31. Two-Level Paging ExampleA logical address (on 32-bit machine with 4K page size) is divided into:
a page number consisting of 20 bits.
a page offset consisting of 12 bits.
Since the page table is paged, the page number is further divided into:
a 10-bit page number.
a 10-bit page offset.
Thus, a logical address is as follows:where pi is an index into the outer page table, and pj is the displacement within the page table.page numberpage offsetpipjd101012
32. Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture Even though time needed for one memory access is quintupled, caching permits performance to remain reasonable